The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2003

Filed:

Nov. 23, 1998
Applicant:
Inventors:

Shoichi Miyamoto, Tokyo, JP;

Yuuichi Hirano, Tokyo, JP;

Takashi Ipposhi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ;
U.S. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ;
Abstract

An SOI substrate ( ) comprises a buried oxide film ( ), an SOI layer ( ) formed on a first region ( ) of the surface ( S) of the buried oxide film, and a silicon oxide film ( ) formed on a second region ( ) of the surface ( S). Formed on the peripheral portion of the SOI layer ( ) is a silicon oxide film ( ), the side surface ( H) of which is integrally joined to the side surface ( H) of the silicon oxide film ( ). The thickness of the peripheral portion of the SOI layer ( ) decreases as closer to the end portion ( H) of the SOI layer ( ), while the thickness of the silicon oxide film ( ) formed on the peripheral portion of the SOI layer ( ) increases as closer to the end portion ( H). A gate oxide film ( ) is formed on a predetermined region of the surface of the SOI layer ( ), and joined to the silicon oxide film ( ) at its end portion. A gate electrode ( ) is then formed on the surface of the gate oxide film ( ) and on a portion where the silicon oxide film ( ) is integrally joined to the gate oxide film ( ). In this manner, an SOI/MOSFET is obtained with no parasitic element formed at the end portion of the SOI layer.


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