The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Dec. 31, 2001
Applicant:
Inventors:
Marcus Kastner, Ottobrunn, DE;
Thomas Mikolajick, München, DE;
Assignee:
Infineon Technologies AG, Munich, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18142 ;
U.S. Cl.
CPC ...
H01L 2/18142 ;
Abstract
The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.
Quick Actions:
Kastner, Marcus. (2003). Integrated semiconductor memory configuration (U.S. Patent No. 6603164). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6603164
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