The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2003
Filed:
Jan. 19, 2000
Applicant:
Inventor:
Tatsuo Teruyama, Kawasaki, JP;
Assignee:
Kabushiki Kaisha Toshiba, , JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/345 ;
U.S. Cl.
CPC ...
G06F 9/345 ;
Abstract
A bypass logic circuit ( ) generates select signals (SelRs , SelRt , SelRs and SelRt ) by using prediction result flags (PrdNTkn A and PrdNTkn D) which are results of prediction about branch, instead of a branch condition not-taken signal (NTknA) actually output from a branch unit ( ). Bypass multiplexers ( ) select operands to be output to ALU ( ) or the branch unit ( ) on the basis of these select signals (SelRs , SelRt , SelRs and SelRt ). Therefore, ample time is given for generating these select signals (SelRs , SelRt , SelRs and SelRt ).