The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6599825 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 29, 2003

Filed:

Dec. 18, 2002
Applicant:
Inventor:

Cheol Soo Park, Kyoungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract

A method for forming wiring in a semiconductor device comprises the steps of: forming a trench in a desired place on a silicon substrate, forming a thermal oxidation layer on the surface of the trench, forming wiring by filling a conductive layer in the lower part of the trench, forming an insulating layer on the wiring, removing the thermal oxidation layer over the insulating layer, forming an epitaxial silicon layer so that the trench is filled completely, forming a contact hole exposing the wiring by etching the epitaxial silicon layer and the insulating layer, forming an insulating spacer on the side walls of the contact hole, and forming a wiring plug in the contact hole in which the insulating layer has been formed. In the method for forming such wiring in the semiconductor device, metal wiring is formed in the silicon substrate.


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