The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2003

Filed:

Feb. 27, 2001
Applicant:
Inventor:

Byung Hak Lee, Choongcheongbuk-Do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
Abstract

A method for fabricating a conductive line pattern for a semiconductor device including the steps of: forming a gate insulation film on the upper surface of a semiconductor substrate; forming a polysilicon layer on the upper surface of the gate insulation film; forming a WNx film on the upper surface of the polysilicon layer; forming a first insulation film on the upper surface of the WNx film; patterning the first insulation film, the WNx film and the polysilicon layer, to form a conductive line pattern; and selectively oxidizing the polysilicon layer. With the method, in view of forming the conductive line pattern in the WNx/poly-Si structure, the thermal treatment processes are reduced in number, so that the thermal stress applied to the conductive line pattern is diminished, and thus, a reliability of the semiconductor device is improved. In addition, as the thermal treatment processes are reduced in number, the processes are simplified, and accordingly a time required for fabricating the conductive line pattern of the semiconductor is decreased.


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