The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2003

Filed:

Dec. 29, 1998
Applicant:
Inventor:

Ynjiun P. Wang, Cupertino, CA (US);

Assignee:

Esignx Corporation, Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 9/30 ; H04L 1/222 ;
U.S. Cl.
CPC ...
H04L 9/30 ; H04L 1/222 ;
Abstract

A computer configured to authenticate a user to an electronic transaction system is disclosed. The computer includes a central processing unit and electronic authorization firmware disposed within the computer and in electronic communication with the central processing unit. The electronic authorization firmware includes a non-volatile memory circuit configured to store at least one of a user private key and user identification data and a firmware identification data. The electronic authorization firmware further includes decryption logic circuitry disposed between the non-volatile memory circuit and the electronic transaction system. The decryption logic circuitry is configured to prevent unauthorized access to at least one of the user private key and the user identification data in the non-volatile memory circuit. The electronic authorization firmware also includes encryption logic circuit coupled to the electronic transaction system and configured to transmit digital data encrypted using the user private key for transmission to the electronic transaction system. The digital data authenticates the user to the electronic transaction system, wherein the non-volatile memory is inaccessible by the central processing unit without traversing the decryption logic circuitry.


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