The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2003
Filed:
Dec. 30, 1999
Zhenguo Gu, Plano, TX (US);
Yuan Kang Lee, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Multiple PN sequences are generated in parallel using multiple LFSRs ( ) or multiple mask circuits ( ) coupled to a single LFSR. The offsets between PN sequences can be individually and independently set, either by setting the initial state in an LFSR ( ) or setting a mask vector in a mask circuit ( ). The LFSRs can be configured in real time to produce one or more blocks of PN sequence bits or to produce disjoint PN sequence bits. Zero insertion may be automatically generated in the LFSRs without additional mask circuitry. PN generating circuits may use either relative or absolute addressing, and may accommodate two levels of relative addressing. Further, one embodiment provides relative addressing without using masks.