The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2003
Filed:
Feb. 13, 2001
Hirokazu Hayashi, Tokyo, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
A semiconductor modeling method capable of simulating impurity pileup at a Si/SiO interface, and analyzing electrical characteristics (for example, substrate bias dependency) of a semiconductor, dependent on impurity concentration, under high speed calculation. A portion of impurities in a Si substrate region is caused to migrate to the Si/SiO interface, there by constituting an impurity pileup part. With such a method, it becomes possible to express the impurity pileups at the Si/SiO interface, which could not be expressed with the use of the conventional Fair model, without finding the solution to diffusion equations associated with point defects, that is without the use of the conventional pair diffusion model.