The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2003

Filed:

Jun. 12, 2002
Applicant:
Inventors:

Satoru Kodaira, Chino, JP;

Masaya Uehara, Chino, JP;

Hitoshi Kobayashi, Nagano-ken, JP;

Takeshi Kumagai, Chino, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 2/900 ; G11C 7/00 ; G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 2/900 ; G11C 7/00 ; G11C 8/00 ;
Abstract

A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.


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