The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2003

Filed:

Apr. 20, 2000
Applicant:
Inventors:

Kyoji Yamasaki, Hyogo, JP;

Takayuki Miyamoto, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 ;
U.S. Cl.
CPC ...
G11C 5/02 ;
Abstract

A memory chip includes a plurality of pins. The plurality of pins are divided into two rows for arrangement on the opposite sides of the memory chip. All data I/O pins are arranged on one side surface (in the same row) of a package. In the case of forming a memory module, each chip is arranged such that the data I/O pins may be nearest to a center line of a module substrate parallel to a connect pin group. Thereby, interconnections between the respective memory chips and the connect pins have substantially equal lengths.


Find Patent Forward Citations

Yamasaki, Kyoji. (2003). Semiconductor integrated circuit having a structure for equalizing interconnection lengths and memory module provided with the semiconductor integrated circuit (U.S. Patent No. 6594167). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6594167

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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