The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2003
Filed:
Jul. 26, 2000
Leslie Ronald Avery, Flemington, NJ (US);
Sarnoff Corporation, Princeton, NJ (US);
Abstract
An exemplary embodiment of the invention eliminates the common P-Well in a stacked SCR structure by providing isolated P-Wells. This embodiment is particularly advantageous in electrostatic protection devices (ESD) formed from a plurality of silicon controlled rectifiers connected in series. The isolated P-Wells are formed, in part, by a high voltage CMOS process incorporating a relatively heavily doped retrograde buried N layer that enables the formation of junction isolated P-Wells surrounded by an N-Well. The complete isolation of the P-Well prevents the normal P-Well to P substrate short, enabling more effective triggering of stacked SCRs. Advantages of implementing isolated P-Wells over a common P-Well in a stacked SCR electrostatic protection device, include faster triggering, lower current triggering, and a reduction in the number of triggering structures required. These advantages are desirable for deep sub-micron ESD protection structures.