Method and system for use of a field programmable interconnect within an asic for configuring the asic

Abstract

An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization. Access to these registers can be controlled by a simple muxing structure that allows the FPGA to have direct access to the registers when the chip initialization sequence takes place (Chip_Init signal is asserted) and allows the processor bus to have access after initialization is complete (Chip_Init signal is de-asserted).