The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2003
Filed:
Aug. 23, 2001
Hideaki Tsuchiko, Santa Clara, CA (US);
Bruce Lee Inn, San Jose, CA (US);
Marty Garnett, Los Gatos, CA (US);
Phillip Fischer, Campbell, CA (US);
Micrel, Inc., San Jose, CA (US);
Abstract
A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being greater than the first distance. In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, the fourth distance being greater than the third distance. The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.