The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2003
Filed:
Sep. 26, 2000
Akihiro Asahina, Tokyo, JP;
NEC Electronics Corporation, Kawasaki, JP;
Abstract
A floorplan design unit lays out a plurality of functional blocks of a semiconductor integrated circuit in a predetermined area. Paths of clock lines in the functional blocks are designed so that clock skew of each functional block satisfies predetermined conditions. A wiring eraser erases clock lines in the functional blocks laid out in the predetermined area. An on-circuit wiring layout unit determines paths of clock lines in the functional blocks from which the clock lines are erased, and determines paths of clock lines among the functional blocks so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions. The on-circuit wiring layout unit determines the clock line paths over the semiconductor integrated circuit with targeting an upper wiring layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile