Separate byte control on fully synchronous pipelined sram

Abstract

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address. No “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.