The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2003
Filed:
Mar. 17, 2000
Thad J. Genrich, Aurora, CO (US);
Raytheon Company, Lexington, MA (US);
Abstract
A parallel asynchronous sample rate reducer ( ) for converting a synchronous parallel digital input signal (INP_DAT) into a parallel digital output signal (OUT_DAT) having an average aggregate sample rate that is asynchronous with respect to the input sample clock rate. The sample rate reducer ( ) includes a parallel phase accumulator ( ) for determining the output sample number values and the fractional phase values corresponding to each output sample number combined in an output value (PHS_ACC). Control logic ( ) receives the phase accumulator output value PHS_ACC and generates an interpolator value (CTL_INT) for controlling interpolation of the input data to interpolate the data to the predetermined output sample number and the corresponding fractional phase values. The control logic ( ) also generates control a build value (CTL_BLD) to enable alignment of the interpolated data signals. A parallel interpolator ( ) receives the input samples and the interpolator control value (CTL_INT) to generate a parallel interpreted data signal (PAR_INT) of the samples. A parallel word builder ( ) then erases invalid samples and compresses samples to the output data word (OUT_DAT) of consecutive, valid samples.