The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2003

Filed:

May. 13, 2002
Applicant:
Inventor:

Luan M. Vu, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/02 ;
U.S. Cl.
CPC ...
G05F 3/02 ;
Abstract

Cascoded transistors can be used to allow circuits to operate at higher operating voltages than the voltages at which individual transistors (formed by a given process) can function. However, common techniques for cascading transistors result in circuits being unable to operate at lower operating voltages. The present invention dynamically biases cascoded transistors in response to the level of the operating voltage, which can vary. Providing separate dynamic bias voltages for N-type and P-type CMOS devices allows circuits using this technique to achieve a wider operating voltage. The wider operating range makes circuits using this technique readily adaptable to a range of power supplies (e.g., different battery configurations) and applications (e.g., driving displays).


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