The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2003

Filed:

Jul. 12, 2001
Applicant:
Inventors:

Montek Singh, New York, NY (US);

Steven M. Nowick, Leonia, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/900 ; H03K 1/90175 ;
U.S. Cl.
CPC ...
H03K 1/900 ; H03K 1/90175 ;
Abstract

A latchless dynamic asynchronous digital pipeline uses control information for a processing stage from the subsequent processing stage as well as stages further down the pipeline. A first function block in a first processing stage is enabled to enter a first evaluate phase and a first precharge phase in response to a first precharge control signal provided by a second, subsequent processing stage which is asserted upon completion of evaluation by the second processing stage and a second precharge control provided by a third processing stage which is asserted upon completion of evaluation by the third processing stage, such that the first evaluate phase is enabled by at least one of the de-assertion of the first precharge control signal and the assertion of the second precharge control signal, and such that the first precharge phase is enabled by the assertion of the first precharge control signal and the de-assertion of the second precharge control signal. A completion generator on a second processing stage may be provided which is responsive to the second precharge control signal and to the data from the first processing stage, is configured to provide an indication to the first processing stage of the phase for which the second function block has been enabled in parallel with such enablement.


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