The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2003
Filed:
Apr. 14, 1997
Applicant:
Inventor:
Derek Wong, San Jose, CA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/900 ;
U.S. Cl.
CPC ...
H03K 1/900 ;
Abstract
A method of using low voltage-swing clocks ( ) with CMOS latches ( ) and with bi-CMOS latches ( ) and associated circuit structures to reduce power requirements of these circuits compared to conventional CMOS and bi-CMOS circuits. Also, a method of using low voltage-swing clocks ( ) to control CMOS (FIG. ) and bi-CMOS dynamic logic. The power consumption of CMOS and bi-CMOS microprocessors and other chips can be substantially reduced by using low voltage-swing clocks, with savings of up to 60% to 80% of the normal clock power at speeds comparable to using normal latches and dynamic logic gates, with noise margins sufficient for safe operation.