Circuit architecture for performing a trimming operation on integrated circuits

Abstract

A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit ( ) having non-volatile memory elements ( ) and a circuit ( ) for modifying the state of the memory elements ( ), a first multifunctional input pin ( ) whereon a sequence ( ) of trimming data is received, a second multifunctional input pin ( ) whereon a timing signal of the trimming operations is received, and an additional access pin ( ) for switching the circuit architecture operation from a normal mode over to a trimming mode. This circuit architecture further includes a volatile memory unit ( ) associated with the non-volatile memory unit ( ) for storing the non-volatile memory ( ) state at power-on or at a simulating phase, and storing the sequence ( ) of trimming data at a programming phase; an interface ( ) is provided between the first multifunctional input pin ( ), the second multifunctional input pin ( ), and the additional access pin ( ), the at least one non-volatile memory unit ( ), and the volatile memory unit ( ), for initially storing the sequence of trimming data ( ) into the volatile memory unit ( ) and subsequently timing the trimming operation.