Memory cell with self-aligned floating gate and separate select gate, and fabrication process

Abstract

Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the shallow and deep diffusion regions of the stack transistor. The memory cell in which the control gate is self-aligned with the floating gate is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, forming shallow and deep diffusion regions along the two edges of the floating gate in the silicon substrate, and forming source and drain regions in the silicon substrate by lightly doped diffusion (LDD) implantation for the select transistors. The memory cell in which the control gate is not self-aligned to the underlying floating gate is formed by patterning the floating gate before the patterning of the control gate and the select gate. The memory cells can be operated in the bit-erasable or byte-erasable EEPROM mode when the deep diffusion region is along one side of the floating gate facing the adjacent select gate, and in page-erasable or sector-erasable flash memory mode when the deep diffusion region along the side of the floating gate opposite the adjacent select transistor.