The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2003
Filed:
Apr. 23, 2002
Applicant:
Inventors:
Adam Aleksan Kablanian, San Jose, CA (US);
Deepak Sabharwal, Fremont, CA (US);
Assignee:
Virage Logic Corp., Fremont, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract
A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.