The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2003

Filed:

Jul. 03, 2001
Applicant:
Inventor:

Joseph G. Petrofsky, Los Gatos, CA (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 3/00 ;
U.S. Cl.
CPC ...
H03M 3/00 ;
Abstract

The present invention relates to analog computation circuits that use a synchronous demodulator topology which can be configured to perform arithmetic computation, power measurements, and/or energy measurement of various analog signals. The computation circuits have circuitry that generates an output signal based on the values of a first input signal, a second input signal, and a reference signal. This invention provides accurate computation of two signals by using modulation circuitry (e.g., &Dgr;-&Sgr; modulation circuitry), demodulation circuitry (e.g., multiplying digital-to-analog converters), delay circuitry, and output circuitry.


Find Patent Forward Citations

Petrofsky, Joseph. (2003). Analog computation circuits using synchronous demodulation and power meters and energy meters using the same (U.S. Patent No. 6587061). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6587061

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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