The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2003
Filed:
Oct. 17, 2001
Patrick H. Buffet, Essex Junction, VT (US);
Yu H. Sun, Beaverton, OR (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An electrical bus grid ( ) for an application specific integrated circuit (ASIC) chip ( ). The bus grid is generally formed by mutually orthogonal wires ( ′) contained within two metal layer (M ′, M ′). The bus grid is located within each of a plurality of contiguous rectangular regions ( ′), which are defined by electrical contacts ( ′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., ) within the ASIC chip.