Dram cell configuration whose memory cells can have transistors and capacitors with improved electrical properties

Abstract

Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches. Above the recess, an insulating structure is preferably disposed in the first indentation and adjoins two adjacent ones of the insulation trenches.