The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2003

Filed:

May. 30, 2001
Applicant:
Inventors:

Yoshitaka Aiba, Kawasaki, JP;

Mitsutaka Sato, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ;
Abstract

A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.


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Aiba, Yoshitaka. (2003). Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal (U.S. Patent No. 6586273). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6586273

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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