The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2003

Filed:

Sep. 24, 2001
Applicant:
Inventors:

Patrick H. Buffet, Essex Junction, VT (US);

Charles S. Chiu, Essex Junction, VT (US);

Yu H. Sun, Williston, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 1/710 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 1/710 ;
Abstract

Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.


Find Patent Forward Citations

Buffet, Patrick. (2003). Method of designing a voltage partitioned solder-bump package (U.S. Patent No. 6584596). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6584596

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…