The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2003
Filed:
Dec. 14, 1999
Applicant:
Inventors:
Akihiro Yamato, Hadano, JP;
Kei Yamamoto, Zama, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/100 ;
U.S. Cl.
CPC ...
G06F 1/100 ;
Abstract
For use in a multiprocessor system in which a plurality of processors share a main memory via a processor bus, an error processing unit (EU) that determines an error level is provided in each processor. When an L2 cache control unit (SU) that controls an L2 cache in the write-back mode, a bus interface unit (PU), and so on, are normal and snoop processing may be continued, the snoop processing is continued in the processor, in which an error occurred, regardless of whether or not the processor is reset. This prevents the system from going down even when data coherence among L2 caches is lost due to an error that occurs in one of processors.