System and method for predicting design errors in integrated circuits

Abstract

The present invention is embodied in a system and method for predicting design errors, such as errors in integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), to predict design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Prediction of design errors is based on a probabilistic comparison of conditions or error symptoms in the current design, to similar or identical conditions or error symptoms associated with design errors identified in prior designs. In addition, the system and method of the present invention is capable of rolling forward in a design from the point where conditions or error symptoms are predicted to analyze the effect such conditions or symptoms may have on the overall design functionality and performance, and whether such conditions and symptoms are actually caused by or will produce design errors. In other words, the system and method of the present invention predicts known errors that have a probabilistic chance of occurring under known conditions and during known tasks, new errors with a probabilistic chance of occurring due to new conditions during a known task, and new errors that have a probabilistic chance of occurring due to new errors that have already happened or have already been predicted.