Non-volatile memory architecture and method of operation

Abstract

In accordance with an embodiment of the present invention, an array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline. Each of a plurality of data lines is coupled to the drain region of at least a portion of a column of cells. Each of a plurality of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells, wherein injection of hot electrons from a portion of the channel region near the source region to the floating gate is induced in a selected memory cell in the array by applying a first voltage to a selected data line to which the drain of the selected memory cell is coupled, a second positive voltage to a word line to which the selected gate of the selected memory cell is coupled, and a third positive voltage to a source line to which the source of the selected memory cell is coupled, wherein the injection of hot electrons increases a threshold voltage of the selected cell.