The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2003

Filed:

Dec. 28, 2001
Applicant:
Inventors:

Dong Suk Shin, Kyoungki-do, KR;

Yong Sun Sohn, Kyoungki-do, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, US;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract

A method of fabricating a semiconductor device having the steps of forming an isolation layer in a silicon substrate to define an active region and a device isolation region; forming a junction region in the active region of the silicon substrate; forming an interlayer dielectric layer on the silicon substrate; forming a contact hole exposing the junction region by selectively removing the interlayer dielectric layer; selectively removing an exposed portion of the junction region under the contact hole; sequentially forming a thin metal layer and a buffer layer on the resultant structure including over the selectively removed portion of the junction region; and forming a silicide layer in the selectively removed portion of the junction region by performing a heat treatment.


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Shin, Dong. (2003). Method of fabricating a semiconductor device having reduced contact resistance (U.S. Patent No. 6583052). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6583052

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