The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2003
Filed:
Oct. 02, 2001
Method for power routing and distribution in an integrated circuit with multiple interconnect layers
Francisco A. Cano, Missouri City, TX (US);
David A. Thomas, Missouri City, TX (US);
Clive Bittlestone, Los Gatos, CA (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level M a second set of power buses and on interconnect level M and a third set of power buses and on interconnect level M The set of power buses on level M are oriented in the same direction as the set of power buses on level M and both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M -M power vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M -M power vias. Dummy cell with M -M power vias is positioned as needed so as not to exceed a maximum strapping distance D A maximum value for distance D is selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.