The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2003
Filed:
Aug. 17, 2001
Sachin Chopra, Santa Clara, CA (US);
Kong-Fai Wo, San Jose, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old routes, and generating a second netlist for a second router design tool using new routing information which excludes the masked old routes. In an exemplary use, the first routing tool is an older tool, while the second routing tool is a newer tool that can provide a more compact database and more efficient routing. The first routing tool may use a format (e.g., ASCII) which is different from the format used by the second router design tool (e.g., binary). In such a case, the channel abstraction may involve extracting all channel routes from the first format, and converting the extracted channel routes into the second format. New routes can be established using the second router design tool based on the second netlist, while preserving other old routes. Abstraction can be achieved by removing from the first netlist selected logic cells which are to be interconnected by the new routes.