Method and apparatus for extracting parasitic element of semiconductor circuit

Abstract

A reference degree of wire congestion relating to the arrangement of fill-metal (or dummy wire) is pre-set, a degree of wire congestion in each of wiring areas of a semiconductor circuit is calculated, the degree of wire congestion in each wiring area is compared with the reference degree of wire congestion, and it is judged that fill-metal is arranged in a specific wiring area of a low wire congestion. To consider an adverse influence of fill-metal arranged in the specific wiring area in the design of a layout of the semiconductor circuit, an insertion amount of the fill-metal is set according to a wire existence probability of the specific wiring area and a target wire existence probability pre-set, and a circuit layout of the specific wiring area is assumed on condition that the fill-metal having the insertion amount is arranged in the specific wiring area. Thereafter, information of parasitic elements such as wire capacitance and inductance is extracted from the layout of the semiconductor circuit in which the circuit layout of the specific wiring area assumed is included.