Interrupt controller

Abstract

An interrupt controller can execute a faster interrupt service routine after an occurrence of the interrupt by writing branch instructions upon initialization of the computer environment in advance of the actual interrupt. The interrupt controller includes an interrupt mask register that receives, and stores an interrupt on/off instruction from a CPU. An interrupt priority register receives and stores an interrupt priority instruction from the CPU. An interrupt mask circuit unit selectively receives and forwards an interrupt generating signal from peripheral devices in response to an interrupt on/off instruction from the interrupt mask register. A priority determining circuit unit receives the interrupt generating signals from the interrupt mask circuit unit, determines priorities of the interrupt signals in response to the interrupt priority instruction from the interrupt priority register, and forwards an interrupt priority signal to an interrupt terminal of the CPU. An interrupt status register stores information pertaining to the source peripheral device from an interrupt signal output from the priority determining circuit unit, and provides a register selection signal corresponding to the source peripheral device information. An interrupt instruction register stores a branch instruction received from the CPU for use upon reception of the interrupt, and provides an interrupt instruction to the CPU in response to a register selection signal from the interrupt status register. In addition, a bus interface circuit unit transfers an address signal between the CPU and the interrupt controller, and a buffer unit buffers a data signal from the CPU to the interrupt controller.