The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2003
Filed:
Apr. 27, 1999
Yasushi Kubota, Sakurai, JP;
Hajime Washio, Tenri, JP;
Ichiro Shiraki, Tenri, JP;
Kazuhiro Maeda, Tenri, JP;
Yasuyoshi Kaise, Tenri, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M and M are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.