The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2003
Filed:
Dec. 14, 2001
Kerry Bernstein, Underhill, VT (US);
Peter E. Cottrell, Essex Junction, VT (US);
Stephen V. Kosonocky, Wilton, CT (US);
David Meltzer, Wappingers Falls, NY (US);
Edward J. Nowak, Essex Junction, VT (US);
Kevin J. Nowka, Round Rock, TX (US);
Norman J. Rohrer, Underhill, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A differential logic circuit ( and ) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure ( ) that is connected to evaluate transistors ( ). In several embodiments, the outputs of the load transistors ( ) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers ( ) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.