Lsi layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit

Abstract

A migration section conducting process migration for converting first layout according to a first design standard into second layout according to a second design standard and a designated transistor size; an extraction section extracting transistor sizes and parasitic capacitances from the first and the second layout; a delay calculation section calculating first delay time from the transistor size and the parasitic capacitance extracted from the first layout and a driving current value of a transistor based on the first design standard, and calculating second delay time from the transistor size and the parasitic capacitance extracted from the second layout and a driving current value of the transistor based on the second design standard; and an optimum value calculation section calculating an optimum value of the transistor size after the process migration in order that the second delay time becomes equal to the first delay time, are provided.