The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
Nov. 15, 1999
Tatuya Ninomiya, Odawara, JP;
Hidefumi Masuzaki, Hadano, JP;
Hiroyuki Kurosawa, Hiratsuka, JP;
Naoya Takahashi, Yokohama, JP;
Yasuo Inoue, Odawara, JP;
Hidehiko Iwasaki, Hiratsuka, JP;
Masayuki Hoshino, Odawara, JP;
Soichi Isono, Chigasaki, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation. Since plurality of first logical units, the plurality of second logical units, and the plurality of cache memories allow hot replace, the storage system can realize its non-stop maintenance.