The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
May. 07, 1999
Andrei Tcherniaev, Mountain View, CA (US);
Iouri Feinberg, Saratoga, CA (US);
Walter Chan, Milpitas, CA (US);
Jeh-Fu Tuan, Saratoga, CA (US);
An-Chang Deng, Saratoga, CA (US);
Nassda Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state. Selected ones of the subcircuits in each of the plurality of subsets share a same dynamic voltage state, where memory storage for the same dynamic voltage state is shared by the subcircuits in each of the selected ones of the plurality of subsets. Once generated, the hierarchical representation may be used during simulation of the circuit to reduce the number of computations required.