Clock recovery in multi-carrier transmission systems

Abstract

A method and apparatus is provided that computes an optimal estimate of known clock frequency error between the transmitter and receiver using a known pilot signal and the statistics of the noise process. The estimate is computed such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. A tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean. In data mode, a tracking scheme makes uses of variations in frequency domain equalizer taps for determination of clock error estimates, computes a residual clock error estimate different from the clock error estimate generated from pilot channel using training mode scheme, and SNR based combination of errors is computed to obtain clock correction, and a dithering mechanism computes the actual correction to be given to the VCXO such that the residual phase error is maintained at an acceptably low value.