The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2003

Filed:

Feb. 16, 2001
Applicant:
Inventor:

John H. Pasternak, Santa Clara, CA (US);

Assignee:

SanDisk Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect of the invention, charge pump and regulator circuitry is not only provided within each of the memory blocks of a memory system, but also the charge pump and regulator circuits are not used to supply voltage signals to their own memory blocks. Instead, the charge pump and regulator circuits are used to supply voltage signals to other memory blocks.


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Pasternak, John. (2003). Method and system for distributed power generation in multi-chip memory systems (U.S. Patent No. 6577535). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6577535

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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