The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
Oct. 25, 2001
Cyrus C. Cheung, Hercules, CA (US);
Keith D. Au, Woodland Hills, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A system which simplifies the clock tuning process for a clock buffer tree. Essentially, a clock buffer tree is provided where the clock buffer tree includes clock buffers of different strengths. The different strength clock buffers which are in the clock buffer tree have the same pin-out configuration. Hence, it is easy and straightforward to upsize or downsize any of the clock buffers in the clock buffer tree, and it is guaranteed that the new cell will fit into the old cell's slot in the tree. Since none of the nets need to be modified, consistent timing results are achieved. Moreover, the new timing for the modified clock buffer can be anticipated because its wire loading does not change at all. The ease of clock tuning makes it much easier to design clock buffer trees and layouts, and allows the overall design to be completed faster and easier.