Cmos sram cell with prescribed power-on data state

Abstract

A CMOS SRAM cell with prescribed power-on data state having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (T /T ; T /T ) serially connected between V and circuit ground to form a first inverter with a first data node (A) between the two transistors (T /T ) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (B) between the two transistors (T /T ) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (T ) is connected between a bit line (BL) and the first data node (A) and another access transistor (T ) is connected between a complementary bit line (BLC) and the second data node (B) to provide data access thereto. A diode (D) is connected in the gate circuit between the complementary P and N type MOS transistors of one of the two latches to change the gate charge time to assure that each latch will assume a pre-determined state upon power-up. The diode (D) can be implemented in dual work function polysilicon topologies by selectively doping adjacent regions of the single gate level polysilicon with an appropriate polysilicon doping type and concentration for each transistor type to form a PN junction ( ) in the polysilicon ( ). A window or opening ( ) is formed in the silicide strapping layer ( ) to enable the PN junction ( ) operation.