Carbon doped epitaxial layer for high speed cb-cmos

Abstract

A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P buried layer regions, a plurality of N buried layer regions, and a P field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. for a time. The temperature is then increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C. Then an N epitaxial layer is deposited on the carbon-doped epitaxial cap layer at 1080° C. Use of a carbon-doped epitaxial cap layer significantly impedes boron up-diffusion from the lower buried layers into the upper PNP structures.