The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2003

Filed:

Jan. 28, 2002
Applicant:
Inventors:

Shigetaka Tomiya, Kanagawa, JP;

Kenji Funato, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/120 ; H01L 2/136 ;
U.S. Cl.
CPC ...
H01L 2/120 ; H01L 2/136 ;
Abstract

A semiconductor thin film includes an underlying semiconductor layer in which a plurality of facets are arranged, and a selectively grown/buried semiconductor layer formed to cover the underlying semiconductor layer, wherein the facets are formed by planes tilted with respect to the disposition plane of the underlying semiconductor layer. In this semiconductor thin film, threading-dislocations are formed in the selectively grown/buried semiconductor layer in such a manner that each of the threading-dislocations bendingly extends from one of the facets of the underlying semiconductor layer in the direction substantially along the disposition plane of the underlying semiconductor layer, being joined to another of the threading-dislocations bendingly extending from the opposed one of the facets, and bendingly extends from the joined portion in the direction crossing the disposition plane of the underlying semiconductor layer. As a result, low defect density regions are formed in the selectively grown/buried semiconductor layer. Further, since a SiO mask is not buried, a deviation in crystal orientation can be suppressed.


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