The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Sep. 06, 2000
Applicant:
Inventors:
Peter Mikel Pohlenz, Colorado Springs, CO (US);
Stacia Patton, Colorado Springs, CO (US);
Assignee:
Aeroflex UTMC Microelectronics Systems, Inc., Colorado Springs, CO (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A cell generator for UTMC's gate array library of core logic cells is implemented using Cadence® Relative Object Design (ROD) software. The ROD functions use design rules to create and align ROD objects. Design rules can be specified for different foundries and technologies, or can be altered to special design requirements. ROD user-defined handles are created to facilitate internal routing and to accommodate different UTMC architectures. Hierarchy is used to minimize the ROD code, and a Cadence® SKILL Makefile generates the entire library automatically.