The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

Jul. 02, 1999
Applicant:
Inventors:

Tayung Wong, Fremont, CA (US);

Ashok Singhal, Redwood City, CA (US);

Clement Fang, Cupertino, CA (US);

John Carrillo, San Jose, CA (US);

Han Y. Ko, San Jose, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/108 ;
U.S. Cl.
CPC ...
G06F 1/108 ;
Abstract

A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.


Find Patent Forward Citations

Wong, Tayung. (2003). System and method for improving multi-bit error protection in computer memory systems (U.S. Patent No. 6574746). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6574746

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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