The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

Dec. 07, 1999
Applicant:
Inventors:

Shigefumi Odaohhara, Yamato, JP;

Arimasa Naitoh, Fujisawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/30 ;
U.S. Cl.
CPC ...
G06F 1/30 ;
Abstract

Disclosed is a method and apparatus for controlling power consumption of the PC, which is provided with base loads comprising a plurality of components, as well as a CPU including operation modes of “throttling” and “clock-down”. Actual power consumption of the CPU in a certain operation mode varies heavily or widely within a range of maximum power consumption of the CPU. A variation of actual power consumption of the base loads is relatively gentle or mild. Predicted maximum power consumption (Pmax) of the PC is obtained from actual power consumption of the base loads and maximum power consumption in the current operation mode of the CPU. Reference power vales are set up such that they are compared with the Pmax for changing an operation mode to another operation mode. When the Pmax exceeds a reference power vale, the operation mode of the CPU is changed for controlling actual power consumption of the PC.


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