The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

Jul. 28, 1999
Applicant:
Inventors:

James J. Jirgal, Chandler, AZ (US);

David Ross Evoy, Tempe, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 1/300 ;
Abstract

An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit. The bridge is operative to enable compatibility between the processor interface and the bus interface such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.


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